Power semiconductor devices have many industrial applications, such as power amplifiers, power convertors, low noise amplifiers and digital Integrated Circuits (IC) to name a few. Some examples of power semiconductor devices are Schottky diode, Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), Insulated Gate Bipolar Transistor (IGBT) and double diffused Metal-Oxide-Semiconductor Transistor (DMOS). The termination structure of power semiconductor devices often requires a high quality semiconductor oxide layer such as silicon oxide. For medium to high voltage devices, a high quality semiconductor oxide layer that is both deep and wide (for example, of the order of ten microns) is often required to insure a high breakdown voltage (BV) and low leakage current Ilk. While semiconductor oxide layers of thickness around 1 micron can be thermally formed or deposited, it can take more than two hours process time just to form a 0.5 micron thick thermal oxide. Besides being of lower quality, a deposited oxide thickness of a few microns is already considered quite thick in that its dielectric property non-uniformity can be a problem. Manufacturing issues with forming a deep and wide oxide filled trench include processing time, non-uniformity, and high stress levels.
FIG. 8 illustrates U.S. Pat. No. 5,998,833 entitled: “Power Semiconductor Devices having Improved High Frequency Switching and Breakdown Characteristics” by Baliga, granted on Dec. 7, 1999. The disclosed integrated power semiconductor device 300′ includes adjacent DEVICE CELLS region and EDGE TERMINATION region and the integrated power semiconductor device 300′ was stated to have improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance and include MOSFET unit cells with upper trench-based gate electrodes (e.g., 126) and lower trench-based source electrodes (not shown). The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (C.sub.GD) of the MOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation. It is pointed out that, due to the substantial structural difference between the DEVICE CELLS region and the EDGE TERMINATION region, an extra body mask is needed to block body implant (e.g., the implant forming P body region 116) from the EDGE TERMINATION region.
FIG. 9A and FIG. 9B are excerpted from U.S. application Ser. No. 12/637,988 illustrating a procedural portion of simultaneously creating a semiconductor device structure with an oxide-filled large deep trench termination portion and another portion of deep active device trenches. Due to the substantial structural difference between the active device trench top area (ADTTA) 3b and the large trench top area (LTTA) 2b, an extra windowed mask 110b is needed to block processing steps for the ADTTA 3b from affecting the LTTA 2b. Therefore, there exists a continued desire to create a highly functional power semiconductor device with an integrated termination structure that is structurally flexible and also simple to manufacture.